You are here

How is the I2C bus arranged? Part 9

Before we proceed to describe the bus communication protocol, we should note that its established name I2C, as well as the names of the lines (SDA and SCL), are the registered names. The copyright of these names belongs to Philips. Accordingly, the other firms producing chips with 12C interface and indicating its presence in the technical documentation, do that under the developer license. For example, the Microchip Company that specializes in the production of microcontrollers has such a license.

However, the firms that do not have a license produce chips with an interface that is very similar to the 12C, but they do not mark it as the12C. Hence the communication protocol may differ slightly from the standardized one. This is done to ensure the accuracy of the legal relationships. In any case, it is recommended to read the technical documentation when using the analogues of branded microassemblies in the designs.

As it has been said, the master organization is the simplest configuration of the 12C bus. We will begin consideration of the communication protocol with it.

Transfer of any bit via a bus occurs under conditions of sampling SDA data through the SCL line. Let’s assume that the master device set the data bit to "0" or "1" on SDA line. The slave device receives this bit only when the rising edge occurs on the SCL line. Hence follows the first rule of organizing a bus protocol: change of the data on the SDA line can only be done at zero state of the SCL line.

We already know that the bus in its standby mode has high levels on the SDA and SCL lines. But how can slave-devices know that the transfer started and ended? To recognize the beginning and end of the data transfer Start and Stop conditions were introduced in the bus specification. In the original documentation the Start condition is marked as “S”, the Stop condition is marked as “P”.

The Start condition occurs at the falling edge of the signal on the SDA line at one state on the SCL line. Conversely, the Stop condition occurs at the positive edge of the SDA line at one state on the SCL line. These conditions should always be generated by master-devices.