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How is the I2C bus arranged?

Classic variant of exchanging data between any devices lies in the fact that one device transfers the information and the other receives it. The devices may switch roles if it’s necessary, i.e., the data transmitter can be a receiver and, vice versa, the receiver can be a data transmitter. But in any case it is important to clearly identify which device is the main device that sets rules and changes the sequence, and which device is the subordinate.

The devices connected to the I2C bus are also subjected to this principle. One of the devices is master and the others are slave. This arrangement of the bus is called the master arrangement and it is the most typical case.

The master device is usually a microcontroller. It sets the basic data flow in the bus, generates the required time intervals and so on.

The multi-master mode is much more rarely used with the equipment, when several master devices are connected to the same bus.

The complexity of such a bus arrangement lies mainly in the fact that the master devices must decide which of them will work with the slave devices. At the same time only one master device can perform operations on the bus, the rest of the devices must be disabled. Otherwise, there might be a bus conflict. The information may simply not reach the destination and the device operation will be disrupted.

To eliminate bus conflicts, multi-master mode should contain procedures for arbitration and synchronization, which establish the work order of the master devices. We will try to understand how the arbitration and the synchronization of the devices are fulfilled. Let’s pay attention to the classic mode with one master device.

The history of the I2C bus started in 1992, when Philips released its first specification version 1.0. This specification ruled out the possibility of specifying the address of a slave device programmatically as the most difficult procedure. Along with the standard mode of data transfer rate of 100 Kbit/s (low-speed), fast transfer mode with a rate up to 400 Kbit/s (fast-speed) was introduced. The10-bit addressing mode appeared as well.